New Technology of 开云·kaiyun官方网站 Design in Integrated System

New Technology of 开云·kaiyun官方网站 Design in Integrated System
At present, most 开云·kaiyun官方网站 designs of electronIC products are integrated system level designs. The whole project includes hardware design and software development This technological feature brings new challenges to electronic engineers First, how to reasonably divide the system software and hardware functions in the early design stage to form an effective functional structure framework and avoid redundant loopback process; Second, how to design high-performance and high reliability 开云·kaiyun官方网站 quickly Because the development of software largely depends on the implementation of hardware, the design cycle can be shortened more effectively only through the overall design This paper discusses the new characteristics and strategies of system board level design under the background of new technology As we all know, the development of electronic technology is changing with each passing day. The root of this change is mainly the progress of chip technology The transistor process is getting closer to the physical limit and has reached the deep submicron level. Ultra large scale circuits have become the mainstream of chip development This change in technology and scale has brought many new bottlenecks in electronIC design to the entire electronic industry Board level design has also been greatly affected One obvious change is that the types of chip packages are very rich; Secondly, high-density lead packaging and miniaturization packaging have become a fashion to achieve the miniaturization of the entire product, such as the extensive application of MCM technology In addition, the increase of chip operating frequency makes it possible to add system operating frequency These changes inevitably bring many problems and challenges to board level design First, due to the increasing physical limitations of high-density pins and pin sizes, the routing rate is low; Second, due to the increase of system clock frequency, timing, and signal integrity problems; Complete complex, high performance design with better tools
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The design of high-speed digital circuits (i.e., high clock frequency and fast edge) has become the mainstream. The miniaturization and high performance of products must face the problem of distribution effect caused by mixed signal design technology (digital, analog and RF mixed design) on the same board. The new design difficulty makes the traditional design process, design method and CAD tools on PC difficult to meet the current scientific and technological challenges. In this regard, it has become a recognized trend in the industry to transfer the EDA software tool platform from UNIX to NT. Generally, when the signal interconnection delay is greater than 20% of the edge signal flip threshold time, the signal line on the board will show the transmission line effect, that is, the connection is no longer a pure line performance that shows the lumped parameters. On the contrary, it shows distributed parameter effect, which is a high-speed design. In the design of high-speed digital systems, designers must solve the problems of error reversal, signal distortion, real-time sequence and signal integrity caused by parasitic effects. At present, this is also the bottleneck problem that high-speed circuit designers must solve. We can find that in traditional high-speed circuit design, power rule setting and physical rule setting are separated. This brings the following disadvantages: engineers must spend a lot of energy in the early design stage to conduct detaiLED front-end (i.e., logical setting physical implementation) analysis to plan the physical routing strategy to meet the power requirements. High speed effect is a complex topic, and the desired effect cannot be achieved SIMply by controlling the wiring length and parallel lines. Designers are bound to face such difficulties. Physical rules with false components are not applicable to actual wiring, and they must be modified repeatedly to make them practical. After the routing is completed, the post validation tool can be used for analysis. However, if problems are found, engineers must return to the design and make structural or rule adjustments. This is a loopback redundancy process. This will inevitably affect the time to MARKet of the product. When there are only a few or dozens of key networks in the design, the physical rule driven method can well complete the design task; But when there are hundreds or even thousands of wire networks in the design, the physical rule driven method is basic. The design task could not be completed. The development of electronic technology requires new methods and tools to solve the bottleneck problems faced by design. In order to solve the problem of high-speed design driven by physical rules, a bit of industry visionary engaged in the research and development of high-speed digital circuit design EDA tool proposed the concept of real-time power rule driven physical layout three years ago. Reform has been carried out.
Interconnection synthesis is a typical term of real-time power rule driven method, that is, in the process of physical layout and routing, the interconnection synthesizer performs real-time analysis according to power rule constraints, selects routing strategies that meet the requirements of the designer, and makes the design pass. This method integrates power demand and physical realization through interconnection, and fundamentally eliminates the defects of physical rule driven method. Input noise constraint and timing constraint rules in the tool; Timing control layout to meet timing constraints; Perform signal integrity pre optimization; Board level integration to ensure that key networks meet power requirements; Complete the wiring of the public network; Optimization. The power rule driven method can effectively evaluate the quality, detect signal distortion, and determine the matching network topology and appropriate terminal matching structure and resistance value before layout design. After the layout and wiring are completed, post verification can be performed and the waveform can be visually detected using a software oscilloscope. The timing and distortion problems found at this time can be solved by using the routing comprehensive optimization function.
Mixed signal design solution
With the miniaturization of design becoming a fashion, consumers need products with high performance and low price. In order to adapt to market competition, manufacturers require R&D personnel to develop high-performance and low-cost products with different types and functions in the shortest possible time. Products, occupy the market. This brings many new design challenges to designers. For example, digital analog hybrid technology and even RF technology are used on the same substrate to achieve miniaturization design and improve product functions. The mobile phones that are popular all over the world are a typical example. The industry also has corresponding solutions - design team, concurrent design, derivation and design reuse are typical strategies.
Traditional series design
That is to say, after the electronic engineer finishes all the front-end circuit designs, it will be handed over to the physical board level designer to complete the back-end implementation. The design cycle is the sum of circuit design and board level design time. After the miniaturized new concurrent design has become the mainstream design idea and the hybrid technology has been widely used, the tandem design method is somewhat outdated. We must innovate design methods and use powerful EDA tools to assist designers in design to meet the requirements of the timely market. As we all know, it is impossible for each of us to complete all our work in all fields or in a short time. The concept of design group was put forward under this background and has been widely used. Nowadays, many companies adopt the design team approach to collaborative product development. That is, according to the complexity of the design and the difference of functional modules, the whole design is divided into different functional blocks, and different designers and developers design logic circuits and 开云·kaiyun官方网站 boards in parallel; Then at the top level of the design, the final design results of each module are transmitted through the pipeline of "equipment" to synthesize the entire Board Design. This method is called 开云·kaiyun官方网站 design reuse. It is easy to see from this method that it can greatly shorten the design cycle, and the design time is just the sum of the design time of the blocks that occupy a lot of time and the processing time of the back-end interface connection.
Derivative technology
To meet the needs of users at different levels, manufacturers focusing on civil products often need to develop products with different functions and levels to occupy the market In the past, for the development of products with different functions, we often used different design processes to implement them respectively. That is, we used different design data to produce circuit boards with different functions to realize products The disadvantage is that the cost is increased, the design cycle is extended, and the artificial unreliable factors of products are increased Many manufacturers now use derivative technology to solve the above problem, that is, use the same design process data to export products of different functional families, so as to reduce costs and improve the quality of 开云·kaiyun官方网站 boards