The role of 开云·kaiyun官方网站 stack in controlling EMI radiation

The role of 开云·kaiyun官方网站 stack in controlling EMI radiation
This paper discusses the function and design skills of layered layout from a basIC 开云·kaiyun官方网站 board There are many ways to solve the problem of electromagnetic interference Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression spare parts and EMI SIMulation design
开云·kaiyun官方网站 board

Power busbar
The reasonable placement of capacitors with appropriate capacity near the power pins of integrated circuits can make the output voltage of integrated circuits jump quickly. However, this is not the end of the problem. Due to the limited frequency response of the capacitor, it is impossible to generate the harmonic power required to clean and drive the integrated circuit output in the entire frequency band. In addition, the transient voltage generated on the power bus will cause voltage drop on the inductance of the decoupling path. These transient voltages are the main source of common mode EMI interference. How should we solve these problems? In the case of integrated circuits on our circuit board, the power plane around the integrated circuit can be considered as a good high-frequency capacitor, which can collect the energy leaked by discrete capacitors. These capacitors provide high-frequency energy to obtain clean output. In addition, the inductance of the good power supply layer should be SMAll, and the transient signal synthesized by the inductance is also small, so as to reduce common mode electromagnetic interference. Of course, the connection from the power layer to the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster, it is directly connected to the bonding pad where the IC power supply pin is located, which will be discussed separately.
In order to control common mode EMI, the power planes must be a pair of reasonably designed power planes for decoupling and have a sufficiently low inductance. Some may ask, how good is it? The answer to this question depends on the layering of the power supply, the data between layers, and the operating frequency (that is, the function of the rise time of the integrated circuit). Generally, the spacing between power layers is 6mil, the intermediate layer is FR4 data, and the equivalent capacitance of power layers per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance. There are not many devices with a rise time between 100 and 300 ps, but according to the current development speed of integrated circuits, devices with a rise time between 100 and 300 ps will account for a large proportion. For circuits with rise times of 100 to 300 ps, 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use layered technology with layer spacing less than 1 mil and replace FR4 dielectric data with data with very high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300 ps rise time circuits. Although new data and methods may be used in the future, the current common 1 to 3 ns rise time circuit, 3 to 6 mil layer spacing and FR4 dielectric data are usually sufficient to handle high-end harmonics and keep the transient at a sufficiently low level, that is, common mode EMI can be reduced to an abnormally low level. The 开云·kaiyun官方网站 layered stack design example given in this article will assume a layer spacing of 3 to 6 mils.
Electromagnetic mask
From the point of view of signal routing, a good layering strategy should be to place all signal traces on one or more layers near the power source or ground plane. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer should be as small as possible. This is what we call "layering" strategy.
开云·kaiyun官方网站 stacking
What stacking strategies help mask and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer and that a single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power planes will be discussed later.
1) 4-layer board: there are several potential problems in 4-layer Board Design. First of all, for the traditional four layer plate with a thickness of 62 mils, even if the signal layer is in the outer layer and the power layer and the ground layer are in the inner layer, the distance between the power layer and the ground layer is still too large. If there is a cost requirement, consider the following two methods to replace the traditional 4-layer plate. Both solutions can improve EMI suppression efficiency, but only when the component density on the circuit board is low enough and there is enough area around the component (where the copper layer of the required power supply is placed). The outer layer of the 开云·kaiyun官方网站 is the ground plane, and the two intermediate layers are the signal/power layers. The power supply wiring on the signal layer has a wide track, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path low. From the perspective of EMI control, this is an existing 4-layer 开云·kaiyun官方网站 board structure. In the second scheme, the outer layer receives power and ground, and the middle two layers receive signals. Compared with the traditional 4-layer plate, the improvement of this scheme is small, and the interlayer impedance is as bad as that of the traditional 4-layer plate. If the trace impedance is to be controlLED, the above superposition scheme needs to be very careful to route the trace under the power supply and grounding copper island. In addition, copper islands on the power supply or ground plane should be interconnected as closely as possible to ensure DC and low-frequency connections.
2) 6-layer board: if the component density on the 4-layer board is relatively large, 6-layer board is used. However, some stacking schemes in the 6-layer board design are not enough to mask the electromagnetic field and have little effect on the transient signal of the power bus. Two examples are discussed below. For example, the power and ground are located on the second and fifth layers respectively. Due to the high impedance of the copper cladding of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is quite correct. The second example places the power and ground on the third and fourth layers respectively. This design solves the problem of copper cladding impedance of power supply. Due to the poor effectiveness of the electromagnetic masks on the first and sixth layers, differential mode EMI is added. If the number of signal lines on the two outer layers is small and the track length is short (less than 1/20 of the signal harmonic wavelength), the design can solve the differential mode EMI problem. The suppression effect of differential mode EMI is particularly good by filling the non component and non trace areas on the outer layer with copper and grounding the copper clad area (every 1/20 wavelength is an interval). As previously mentioned, the copper area should be connected to the internal ground plane at multiple points. Generally, the first and sixth layers are arranged as ground layers in the design of high-performance Six layer board, and the third and fourth layers are responsible for power supply and ground. Since there are two central double microstrip signal line layers between the power supply and the ground plane, this EMI suppression effect is excellent. The disadvantage of this design is that there are only two layers of traces. As previously mentioned, if the outer layer trace is short and the copper is placed in a traceless area, the same stacking can be achieved using traditional 6-layer plates. Another 6-layer circuit board layout is signal, grounding, signal, power supply, grounding and signal, which can realize the environment required for signal integrity design. The signal layer is adjacent to the ground plane, and the power supply is paired with the ground plane. Obviously, the disadvantage is that the layers are stacked unevenly. This usually brings trouble to the manufacturing industry. The solution to this problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or ground plane after copper filling, the circuit board can be loosely counted as a circuit board with balanced structure. The copper filled area must be connected to power or ground. The distance between connecting vias is still 1/20 wavelength, not necessarily anywhere, but should be connected under ideal conditions.
3) 10 layer circuit board: due to the very thin insulation layer between multilayer circuit boards, the impedance between layers of this 10 layer or 12 layer circuit board is very low. As long as there is no problem with layering and stacking, good signal integrity can be achieved. It is more difficult to manufacture 12 ply plates with a thickness of 62 mils, and there are few manufacturers that can process 12 ply plates.
Since there is always an insulating layer between the signal layer and the loop layer, it is not feasible to assign the middle 6 layers to route signal lines in the 10 layer board design. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the circuit board layout is signal, grounding, signal, signal, power supply, grounding, signal, signal, grounding, and signal. This design provides a good path for signal current and its loop current. The correct routing strategy is to route Layer 1 along the X direction, Layer 3 along the Y direction, Layer 4 along the X direction, and so on. Intuitively, layers 1 and 3 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are a pair of layered combinations. When it is necessary to change the direction of the trace, the signal line on the first layer should be "through-hole" to the third layer, and then change the direction. In practice, this may not always be possible, but as a design concept, try to follow it. Similarly, when the signal routing direction changes, it should pass through the vias from layer 8 and layer 10 or from layer 4 to layer 7. This routing ensures tight coupling between the forward path and the return path of the signal. For example, if the signal is routed on the first layer, the loop is routed on the second layer, and only on the second layer. Even though the signal on the first layer reaches the third layer through the "through-hole", the loop is still on the second layer, thus maintaining low inductance, high capacitance and good electromagnetic shielding efficiency. What if the actual wiring is not like this? For example, the signal line on the first layer passes through the through-hole to reach the tenth layer. At this time, the loop signal must find the ground plane from the ninth layer, and the loop current needs to find the nearest grounding through-hole (such as the grounding pin of resistor or capacitor and other components). If there happens to be such a through-hole nearby, you are really lucky. If there is no such tight through-hole, the inductance will increase, the capacitance will decrease, and the electromagnetic interference will certainly increase. When the signal wire must leave the current pair wiring layer to other wiring layers through the vias, the grounding vias should be placed near the vias so that the loop signal can return to the appropriate grounding layer smoothly. For the layering combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitive coupling between the power layer and ground layer is good, and the signal is easy to transmit.
Multi power layer design
If two power supply planes of the same voltage source need to output large current, the circuit board shall be arranged in two groups of power supply planes and ground plane. In this case, place an insulating layer between each pair of power supplies and the ground plane. Through this pipe, we get two pairs of power buses with equal impedance, and we hope to distribute the current evenly. If the stack of power planes produces unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and the electromagnetic interference will increase significantly. If there are multiple power supply voltages with different values on the circuit board, multiple power planes are required. Remember to create your own paired power supply and ground plane for different power supplies. In both cases, remember the manufacturer's requirements for a balanced structure when determining the position of the matching power supply and ground plane on the circuit board.
Summary
Considering that most engineers design the circuit board as a traditional printed circuit board with a thickness of 62 mils, without blind holes or embedded vias, the discussion on the board level and the board is limited to this. For plates with large thickness difference, the delamination scheme recommended in this paper may not be ideal In addition, the circuit boards with blind holes or embedded vias have different processing pipelines, so the layering method in this paper is not applicable This thickness, via process and the number of layers of the circuit board in the circuit board, is not the key to solve the problem Good layered stacking is to ensure bypass and decoupling of the power bus, so that the transient voltage on the power supply or ground plane is not affected The key to mask signals and power electromagnetic fields Ideally, there should be an insulation isolation layer between the signal tracking layer and its return ground plane, and the distance between this pair of layers (or more than one pair) should be as small as possible. Based on these basic concepts and principles, 开云·kaiyun官方网站 can always meet the design requirements