开云·kaiyun官方网站 Factory: Introduction to 9 Packaging Technologies of SMD

开云·kaiyun官方网站 Factory: Introduction to 9 Packaging Technologies of SMD

Surface Mount Devices (SMDs) are developed on the basis of the original dual in line package (DIP), whICh is an important symbol of the development of through-hole insertion technology to SMT. surface mount devices mainly have the following nine packaging technologies.

(1) SMAll outline transistor

SOT is a surface mount transistor with small package structure, mainly including SOT23, SOT89, SOT143, SOT25, etc. SOT23 is a commonly used triode packaging form. It has three wing shaped pins, namely collector, EMItter and base, which are respectively listed on both sides of the long side of the element. The emitter and base are on the same side. It is commonly used in small power transistors, field effect transistors and composite crystal tubes with resistance networks. It has good strength but poor solderability. Its shape is shown in Figure 2-1 (a). SOT89 has three short pins, which are distributed on one side of the transistor, and the other side is a metal heat sink, which is connected to the base to increase the heat dissipation capacity. It is commonly used in silicon power surface mount transistors and is suitable for high power applications. SOT143 has four short wing shaped pins, which are LED out from both sides. The one with the larger width in the pin is the collector. This type of package is commonly used in high-frequency transistors. SOT252 is a high-power transistor. Three pins are led out from one side. The middle pin is short and is a collector. It is connected to the larger pin at the other end. This pin is a copper sheet for heat dissipation.

(2) small outline Integrated Circuit

SOic package is a surface mounted component package with wing shaped or J-shaped short leads on both sides. SOIC package has two different pin forms: one is SOP with wing pin, and the other is SOJ with J pin.

SOP packages are commonly used in linear circuits, logic circuits, random access memories, etc. The common models are SOP8, SOP14, SOP16, SOP20, SOP24, SOP28, SOP48, SOP56, SOP64, etc. The SOP pin spacing is 1.27mm, 1.0mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm, etc. The number of pins is even and symmetrical.

SOJ is different from SOP in that the pin spacing is only 1.27mm and the number of pins mainly includes 14, 16, 18, 20, 22, 24, 26 and 28. Compared with the wing shaped pin, the J-shaped pin is relatively thick and not easy to deform. The J-shaped pin has certain elasticity, which can relieve the pressure of mounting and welding and prevent the solder joint from cracking.

(3) Plastic Lead chip Carrier

The pins of the PLCC package are bent inward at the bottom of the chip. The J-shaped pin has certain elasticity, which can relieve the installation and welding stress. It is mainly used for computer processing units, special integrated circuits, gate array circuits, etc. PLCC has two types: square and rectangular. There are 20-84 square pins and 18-32 rectangular pins.

(4) Leadless CeramIC chip Carrier

LCCC is a surface mount package with electrode pads on all four sides of the ceramic substrate without pins. The chip is packaged on a ceramic carrier for high-speed and high-frequency integrated circuit packaging. The pin spacing is mainly 1.27mm and 1.0mm. LCCC has two shapes: square shape and rectangular shape, and square shape has two shapes: 16, 20, 21.27mm and 1.0mm. LCCC has two shapes: square and rectangle. The square has 16, 20, 24, 28, 44, 52, 68, 84, 100 and 156 electrodes, and the rectangle has 18, 22, 28 and 32 electrodes.

(5) Quad flat package

QFP is a new type of package developed for IC with small pin pitch, which is suitable for the increase of IC content and I/O quantity. QFP has wing shaped short pins on all four sides. Generally, the chips packaged are large-scale integrated circuits, including square and rectangular ones. The number of electrode pins is at least 28, and the maximum number can reach 576. The common pin spacing is 1.0mm, 0.8mm, 0.65mm, 0.50mm, 0.40mm, 0.3mm, etc. QFP has many pins, large contact area, and high welding strength, but the pins are easy to bend and damage during transportation, storage, and installation, The coplanarity of pins is changed, which affects the coplanar soldering of devices.

With the continuous development of packaging technology, there are shrink quad flat packs (SQFPs), thin

The size of square flat package (TQFP) and ceramic square flat package (CQFP) is smaller than that of traditional QFP, and the thickness of TQFP package has been reduced to 1.0mm or even 0.5mm.

(6) Ball Grid Array (BGA)

BGA is the packaging technology of large-scale integrated circuits. The packaged I/O terminals are distributed under the package in the form of circular or cylindrical solder joints in an array. The common pin spacing is 1.5mm, 1.27mm and 1.0mm. Although the number of I/O pins in the BGA package has increased, the pin spacing has not decreased, but has increased, thus improving the assembly yield. Although its power consumption has increased, the BGA can be welded with the controllable collapse chip method, which can improve its electrical performance. Its thickness and weight are reduced compared with previous packaging technologies. The signal transmission delay is small, and the use frequency is greatly increased. The assembly can be coplanar welding, with high reliability, It greatly improves the assembly process, and is particularly suitable for use in high-frequency circuits. The existing problem is that post welding inspection and maintenance are relatively difficult, and radiographic testing must be used to ensure the reliability of welding; It is easy to absorb moisture and should be dried before use.

BGA is usually composed of chips, substrates, pins and enclosures. BGA can be divided into plastic ball grid array (PBGA), ceramic ball grid array (CBGA), ceramic column grid array (CCGA), tape ball grid array (TBGA), etc. according to different chip positions, pin arrangements, substrate materials and sealing methods.

The PBGA chip faces up and is soldered to the upper surface of the substrate through gold wire. The packaging cost is low, the pin is not easy to deform, the reliability is high, and it is easy to absorb moisture. The ball must be replanted after removal; CBGA is connected on the upper surface of multilayer ceramic substrate, with high electrical, thermal and mechanical properties, good corrosion resistance and moisture resistance. However, when the package size is large, the CTE mismatch between the ceramic and the substrate is easy to cause thermal cycle failure; The CCGA solder column can withstand the stress caused by the difference between components and 开云·kaiyun官方网站s, and the solder column is more vulnerable to mechanical damage than the solder ball during assembly; TBGA uses bimetallic tape as its substrate. The connection between the substrate and the chip is usually realized by flip chip technology. It is small in size, excellent in electrical performance, easy to assemble in batches, good in matching with CTE of 开云·kaiyun官方网站, but easy to absorb moisture, and high in packaging cost.

(7) Chip Scale Package

CSP is the product of further miniaturization of BGA. It reduces the size of chip package. The side length of packaged IC is not more than 1.2 times of the chip, and the IC area is not more than 1.4 times of the grain. It is suitable for memory modules and portable electronic products with few pins. The common pin spacing is 1.0mm, 0.8mm, 0.65mm and 0.5mm.

CSP provides shorter interconnects than QFP, has better electrical performance, is more suitable for high-frequency applications, is smaller than BGA, is more flat, and is conducive to improving the quality of reflow soldering. The body is thin, so it has better heat dissipation performance. However, there are problems with solder joint quality detection and thermal expansion coefficient matching.

(8) Chip on Board

COB is to adhere the bare chip to the interconnection substrate with conductive or non-conductive adhesive, and then conduct lead bonding to realize its electrical connection. The welding area and the chip body are on the same plane, with uniform distribution around, and the minimum spacing is 0.1mm. Wire bonding is used to weld the lead and 开云·kaiyun官方网站 pad, and epoxy resin is used to encapsulate and protect the bonding lead.

COB is not suitable for automatic mounting in large quantities, and the manufacturing process for COB method is relatively difficult, and heat dissipation is also difficult, which is usually applicable to low power IC chips.

(9) Flip Chip

Flip chip packaging technology was developed by IBM in 1960. In order to reduce cost, improve speed, and improve component reliability, FC is used in the first layer of chip and carrier board bonding packaging. The packaging method is that the chip faces down to the substrate, without wire bonding, to form the shortest circuit and reduce resistance; The metal ball connection is adopted to reduce the package size, improve the electrical performance, and solve the problem that BGA needs to expand the volume to increase the number of pins.

FC is usually applied to CPU with high time pulse or RF with high frequency to obtain better efficiency. Compared with traditional wire bonding technology with slow speed, FC is more suitable for products with high pin count, miniaturization, multi-function and high speed trend IC.

开云·kaiyun官方网站 manufacturers, 开云·kaiyun官方网站 designers and 开云·kaiyun官方网站A manufacturers will explain the 9 packaging technologies of SMD.