Writing Skills of 开云·kaiyun官方网站 Design Rule Checker

Writing Skills of 开云·kaiyun官方网站 design Rule Checker
This paper briefly introduces a rule checker (DRC) system for 开云·kaiyun官方网站 design Once the 开云·kaiyun官方网站 is designed using the schematIC generation tool, you can run DRC to find violations of 开云·kaiyun官方网站 design rules Before starting subsequent processing, these operations must be completed. Developers of schematic generation tools must provide 开云·kaiyun官方网站 designers with DRC tools that can be easily accessed by most people
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Writing 开云·kaiyun官方网站 design rule checker has many advantages Although the 开云·kaiyun官方网站 design checker is not that SIMple, it is not impossible, because any 开云·kaiyun官方网站 designer who is familiar with the existing programming or script language can check 开云·kaiyun官方网站 design The benefits of this work are incalculable However, the general tools sold on the MARKet are usually not flexible enough to meet specific 开云·kaiyun官方网站 design requirements Therefore, customers must reflect new functional requirements to DRC tool developers, which usually requires a certain amount of money and time, especially when requirements are constantly updated Fortunately, most tool developers provide a convenient channel for customers to write their own DRC to meet specific needs However, this powerful tool has not yet been widely recognized or used This article provides a practical guide to using DRC tools to gain benefits
Because DRC must traverse the entire circuit diagram of 开云·kaiyun官方网站 design, including each symbol, each pin code, each network, and each content. If necessary, an unlimited number of "additional" files can be created As described in Section 4 0. The Democratic Republic of the Congo can mark any violation of 开云·kaiyun官方网站 design rules For example, one of the attached files may contain all decoupling capacitors used in 开云·kaiyun官方网站 design If the number of capacitors is lower or higher than the expected value, there will be a red mark/dt problem where there may be power line dv These profiles may be necessary, but not all commercial DRC tools can create them Another advantage of DRC is that it can be easily updated to meet new requirements 开云·kaiyun官方网站 design features (such as those that may affect 开云·kaiyun官方网站 design rules) In addition, many other functions can be implemented once sufficient experience is gained in this field For example, if you can write your own DRC, then you can write your own bill of material (BOM) creation tool, it can better handle specific user needs Or 开云·kaiyun官方网站 designers can write their own Verilog netlist analyzer, which has sufficient flexibility in the following aspects: 开云·kaiyun官方网站 design environment, for example, how to obtain Verilog models or time files suitable for specific devices In fact, since DRC traverses the entire 开云·kaiyun官方网站 design circuit diagram, it can collect all effective information to output BOMs required for analog and/or 开云·kaiyun官方网站 design verilog netlist analysis It is far fetched to discuss these topics without providing any code. After all, we will use the circuit diagram acquisition tool as an example This article uses the ViewDraw tool developed by Mentor Graphics to connect to the PADS Designer product line In addition, we have adopted the ViewBase tool, which can be calLED to access the simplified C routine library of the ViewDraw database With the ViewBase tool, 开云·kaiyun官方网站 designers can easily use the C/C language to write a complete and efficient DRC tool for ViewDraw [2] [3] It should be noted that the basic principles discussed here also apply to any other 开云·kaiyun官方网站 drawing tool
Put file in
In addition, to the circuit diagram database, DRC also needs some input files, which can describe the specific situations to be handled, such as automatically connecting to the power plane using a valid grid name For example, if the power grid is named power, then the power plane will be automatically connected to the power plane using a backend package device (eg, fwd开云·kaiyun官方网站 boards of ViewDraw) A list of input files is given below. These files must be placed in a fixed global location so that DRC can automatically find and read them, and then store the information in DRC at runtime Some symbols must have external power cord pins because they are not connected to the regular power cord layer For example, VCC pin of ECL device can be connected to VCC or ground; Its V-pin can be grounded or - 5.0V plane In addition, the power line pin can also be connected to the filter before reaching the power line layer The power cord pin is usually not externally connected to the device symbol On the contrary, an attribute of the symbol (called SIGNAL here) describes which pin is a power or ground pin and describes the net name that the pin should be connected to
The DRC can read this content and ensure that the network name is saved in the legal  u pwr  u net  u name file. If the network name is not included in the legal  u pwr  u net  u name, the power pin will not be connected to the power board, which is a serious problem The file legal  u pwr  u net  u name is optional. The file contains all the legal network names of the power signal, such as VCC, V3_ 3P and VDD In 开云·kaiyun官方网站 layout/wiring tool, it is necessary to distinguish case names Generally, VCC is not equivalent to VCC or VCC VCC can be a 5.0V power supply, while V3  u 3P can be a 3.3V power supply The file legal  u pwr  u net  u name is optional because the backend wrapper device profile must usually contain a combination of powerline network names If the Allegro routing tool 开云·kaiyun官方网站 board of CADence uses the design system company, the file name 开云·kaiyun官方网站 board fwd is Allegro Cfg and have the following input parameters: Ground: VSS CGND GND Ground Power supply: VCC VDD VEE V3  U 3P V2  U 5P 5V 12V If the Democratic Republic of the Congo can read Allegro Use cfg files directly instead of legal_ pwr_ net_ name, it will get better results (ie less chance of introducing errors).

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